Credits: 3 (3-0-0)
Description
VLSI Scaling rules and their impact: Short channel effect, Sub threshold leakage current, Gate leakage, VTH and body bias; Low power design: Technology level: 3D and 4 terminal MOSFETs, PDSOI, FDSOI, FINFET; Sub threshold leakage control: Transistor stacking in digital logic Multiple VTH, VDD designs, Dynamically adjustable VTH; Digital Circuit Design: Digital Sub-threshold Logic, Noise Immunity, Clock gating, Switching activity minimization; Analog Circuit Design: gm/ID Methodology for Design, Low power, low voltage opamp design, Subthreshold operation of opamps; Architecture level: Array Based Architectures, Parallel and Pipelined Architectures; Interconnects & Noise: Capacitive & Inductive coupling Analysis & Optimization, Power/Ground Noise, L*di/dt noise, Power/Ground Placement Optimization, Decoupling.